1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device in which a plurality of memory cells are implemented by field effect transistors (FETs) each having a floating gate and arranged in a matrix and within which programming of the memory cell transistors is performed row by row.
2. Description of the Related Art
Non-volatile semiconductor memory devices include a flash memory having a plurality of memory cell transistors implemented by FETs each having a floating gate and arranged in a matrix, i.e., in row and column directions. Recently, the memory capacity of such a non-volatile semiconductor memory device has been increased more and more, and hence writing data therein is executed row by row to reduce the length of time required for the writing (programming). This type of the non-volatile semiconductor memory device is described in ISCC94, SESSION 8, "DRAMS AND NON-VOLATILE MEMORIES", PAPER TA 8.6 by H. Sugawara et al, for example.
FIG. 1 shows an example of such a conventional non-volatile semiconductor memory device, while FIG. 2 shows a timing chart thereof wherein waveforms for a single block in the memory cell array in FIG. 1 are shown, the memory cell array includes x blocks arranged in a row direction and each including k bit lines (BL.sub.1 --BL.sub.k, for example).
In a programming operation, data signals DI.sub.1 --DI.sub.x each of a k-bit data are supplied from outside the memory device as the data to be stored, which are latched by shift registers SR.sub.1a --SR.sub.xa through data-in buffer sections (blocks) DIB.sub.1 --DIB.sub.x in accordance with a data fetch signal DGET output from a timing control section 7a.
In response to a first level (a low level) of a write control signal PROG, a timing control section 7a starts to generate an internal clock signal ICK, and the level of a selected word line Wi.sub.l is changed to assume a selection level. An internal address generating section 9 generates an internal address signal ADI for specifying an internal address within each of the blocks in the memory cell array 1. The address indicated by the internal address signal ADI is successively updated synchronously with the internal clock signal ICK so that the specified internal address advances in a cyclic order.
A column address buffer section 4 receives the internal address signal ADI and transmits the same to a column decoder 5a. The column decoder 5a decodes the internal address signal ADI so as to successively change column selection signals Y.sub.1 --Y.sub.k on respective output lines thereof so that one of the k column selection signals Y.sub.1 --Y.sub.k assumes a selection level. A column selecting circuit 6 connects one of the bit lines BL.sub.1 to BL.sub.k, in response to one of the column selection signals Y.sub.1 --Y.sub.k having the selection level, to the output of, the corresponding write control section WA.sub.1 --WA.sub.x.
Data signals DI.sub.l to DI.sub.x latched in shift registers SR.sub.1a --SR.sub.xa are transmitted along the shift registers SR.sub.1a --SR.sub.xa and through the output end of the shift register (e.g., SR.sub.1a) to the write control section (e.g., WA.sub.1) synchronously with the internal clock signal ICK. The write control section (e.g., WA.sub.1) controls the potential of the corresponding block of the bit lines BL.sub.1 to BL.sub.k in accordance with the level of the data signal transmitted thereto.
When one of the data signals has a high level for programming a specified memory cell transistor into a programmed state, the potential of the corresponding bit line (e.g., BL.sub.1) is controlled to have a programming potential Vp. When the data signal has a low level for allowing the memory cell transistor to hold an erased state, the corresponding bit line is left at a floating state. In FIG. 2, for the sake of simplification, a specific case is shown in which each of the data signals DI.sub.1 --DI.sub.k has a high level for programming.
The potentials on the bit lines can be maintained by respective parasitic capacitance of the bit lines etc. for a while, and are gradually lowered due to programming current requiring electric charge. To recover the potentials, the write control sections WA.sub.1 to WA.sub.x periodically refresh the potentials of the respective bit lines BL.sub.1 to BL.sub.k during the programming period while a write control signal PROG is maintained at the first level, so that the bit lines BL.sub.1 --BL.sub.n are maintained at potentials corresponding to the programming level during each programming period. In this way, the programming for the row is executed corresponding to the data signal for the memory cell transistors connected to a selected word line (e.g., WL.sub.1).
Thereafter, in response to a change in the level of the write control signal PROG from the first level to a second level, the generation of clock pulses in the internal clock signal ICK and hence the internal address signal ADI are stopped. As a consequence, all the levels of the column selection signals Y.sub.1 --Y.sub.k from the column decoder 5a assume the selection level for a predetermined length of time, and all the levels at the outputs of the write control sections WA.sub.1 --WA.sub.x assume the ground potential. Accordingly, the levels of the bit lines BL.sub.1 --BL.sub.n are reset to the ground potential, whereby the programming operation for one row of the memory cell transistors is completed.
In the above-mentioned conventional non-volatile semiconductor memory, there is a problem in that the threshold voltage varies among the memory cell transistors after completion of the programming as described above so that reliable programming cannot be effected in the memory device.